Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs (2025) Esper K, Wildermann S, Teich J Conference contribution JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs (2024) Hahn T, Wildermann S, Teich J Conference contribution, Conference Contribution OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers (2024) Heidorn C, Hannig F, Riedelbauch D, Strohmeyer C, Teich J Conference contribution, Conference Contribution Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs (2024) Esper K, Wildermann S, Teich J Conference contribution, Original article ALPACA: An Accelerator Chip for Nested Loop Programs (2024) Walter D, Brand M, Heidorn C, Witterauf M, Hannig F, Teich J Conference contribution, Conference Contribution OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers (2024) Heidorn C, Hannig F, Riedelbauch D, Strohmeyer C, Teich J Other publication type Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks (2024) Heidorn C, Sabih M, Meyerhöfer N, Schinabeck C, Teich J, Hannig F Journal article CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets (2024) Krüger P, Wildermann S, Teich J Conference contribution, Conference Contribution ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs (2024) Hahn T, Schüll D, Wildermann S, Teich J Conference contribution, Conference Contribution History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs (2024) Esper K, Teich J Conference contribution, Conference Contribution