Automatic Cross-Layer Synthesis of High Performance, (Ultra-)Low Power Hardware Implementations from Data Flow Specifications by Integration of Emerging FeFET Technology (HiLoDa Nets)
Third party funded individual grant
Acronym:
HiLoDa Nets
Start date :
01.03.2024
End date :
01.03.2027
Website:
https://www.cs12.tf.fau.de/forschung/projekte/hiloda-nets/
Filters (inactive)
Exploration of Clock and Power Gating Tradeoffs for the Design of Self-Powering Dataflow Networks (2025)
Karim A, Falk J, Teich J
Conference contribution, Conference Contribution
Self-Powering Dataflow Networks – Concepts and Implementation (2024)
Karim A, Falk J, Schmidt D, Teich J
Conference contribution, Conference Contribution
Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems (2024)
Letras M, Falk J, Teich J
Journal article, Online publication
Techniques for Efficient Performance Analysis and Memory Optimization in Mapping Dataflow Models of Computation onto Embedded Systems (2024)
Letras M
Thesis
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications (2023)
Henkel J, Sidduh L, Bauer L, Teich J, Wildermann S, Tahoori MB, Mayahinia M, et al.
Conference contribution, Original article