Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Efficient Computation of Probabilistic Dominance in Multi-objective Optimization (2021) Khosravi F, Raß A, Teich J Journal article LION: Real-Time I/O Transfer Control for Massively Parallel Processor Arrays (2021) Walter D, Teich J Conference contribution, Conference Contribution Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs using Accuracy-Programmable Instruction Set Processors (2021) Schuster A, Heidorn C, Brand M, Keszöcze O, Teich J Conference contribution, Conference Contribution Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs (2021) Spieck J, Wildermann S, Teich J Conference contribution, Conference Contribution Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits (2021) Traiola M, Echavarria Gutiérrez JA, Bosio A, Teich J, O'Connor I Conference contribution, Original article Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems (2021) Brand P, Falk J, Potwigin E, Teich J Conference contribution, Conference Contribution Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays (2021) Heidorn C, Walter D, Candir YE, Hannig F, Teich J Conference contribution, Abstract of lecture Symbolic Loop Compilation for Tightly Coupled Processor Arrays (2021) Witterauf M, Walter D, Hannig F, Teich J Journal article, Original article CHOICE – A Tunable PUF-Design for FPGAs (2021) Streit FJ, Krüger P, Becher A, Schlumberger J, Wildermann S, Teich J Conference contribution, Conference Contribution On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains (2021) Echavarria Gutiérrez JA, Wildermann S, Keszöcze O, Khosravi F, Becher A, Teich J Other publication type