Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures (2005) Dutta H, Hannig F, Teich J Other publication type The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform (2005) Ahmadinia A, Bobda C, Fekete SP, Haller T, Linarth AG, Majer M, Teich J, Van Der Veen JC Conference contribution Output Serialization for FPGA-based and Coarse-grained Processor Arrays (2005) Hannig F, Teich J Conference contribution Increasing the Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine (2005) Ahmadinia A, Bobda C, Haller T, Linarth AG, Majer M, Teich J Conference contribution A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices (2005) Ahmadinia A, Bobda C, Ding J, Fekete SP, Majer M, Teich J, Van Der Veen JC Conference contribution Verteilte HW/SW-Partitionierung für fehlertolerante rekonfigurierbare Netzwerke (2005) Streichert T, Haubelt C, Teich J Conference contribution Initial Population Construction for Convergence Improvement of MOEAs (2005) Haubelt C, Gamenik J, Teich J Book chapter / Article in edited volumes Comparison of Techniques for the Automatic Verification of ADeVA Specifications (2005) Dinkel T, Haubelt C, Heinkel U, Schlichter T, Knäblein J, Schock T, Teich J Conference contribution Modeling and analysis of indirect communication in Particle Swarm Optimization (2005) Helwig S, Haubelt C, Teich J Conference contribution, Conference Contribution Improving EA-based design space exploration by utilizing symbolic feasibility tests (2005) Schlichter T, Haubelt C, Teich J Conference contribution, Conference Contribution