Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

FPGA Core Watermarking Based on Power Signature Analysis (2006) Ziener D, Teich J Conference contribution Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays (2006) Hannig F, Merker R, Siegel S, Teich J Conference contribution Bridging the Gap between Relocation and Available Technology: The Erlangen Slot Machine (2006) Göhringer D, Majer M, Teich J Conference contribution Are Current ESL Tools Meeting the Requirements of Advanced Embedded Systems? (2006) Teich J Conference contribution A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing (2006) Dutta H, Hannig F, Heigl B, Hornegger H, Teich J Conference contribution Efficient Representation and Simulation of Model-Based Designs in SystemC (2006) Falk J, Haubelt C, Teich J Conference contribution A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template (2006) Kissler D, Hannig F, Kupriyanov O, Teich J Conference contribution Improving system level design space exploration by incorporating SAT-solvers into multi-objective evolutionary algorithms (2006) Schlichter T, Lukasiewycz M, Haubelt C, Teich J Conference contribution, Conference Contribution A highly parameterizable parallel processor array architecture (2006) Kissler D, Kupriyanov O, Hannig F, Teich J Conference contribution, Conference Contribution Higher-dimensional packing with order constraints (2006) Teich J, Fekete SP, Köhler E Journal article