Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Auto-Tuning of Raw Filters for FPGAs (2022) Hahn T, Wildermann S, Teich J Conference contribution, Conference Contribution Multi-requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study (2022) Esper K, Wildermann S, Teich J Conference contribution, Conference Contribution DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks (2022) Sabih M, Hannig F, Teich J Conference contribution, Conference Contribution Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems (2022) Pourmohseni B, Wildermann S, Smirnov F, Meyer P, Teich J Journal article Raw Filtering of JSON data on FPGAs (2022) Hahn T, Becher A, Wildermann S, Teich J Conference contribution, Conference Contribution Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks (2022) Sommer J, Özkan MA, Keszöcze O, Teich J Conference contribution, Original article On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures (2022) Spieck J, Wildermann S, Teich J Conference contribution, Conference Contribution TRAC: Compilation-based Design of Transformer Accelerators for FPGAs (2022) Plagwitz P, Hannig F, Teich J Conference contribution, Conference Contribution DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks (2022) Sommer J, Özkan MA, Keszöcze O, Teich J Conference contribution, Original article Real-Time Waveform Matching with a Digitizer at 10 GS/s (2022) Trautmann J, Patsiatzis N, Becher A, Teich J, Wildermann S Conference contribution, Conference Contribution