Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

SYSTEMCODESIGNER - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications (2009) Keinert J, Streubühr M, Schlichter T, Falk J, Gladigau J, Teich J, Haubelt C, Meredith M Journal article, Original article Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures (2009) Kissler D, Strawetz A, Hannig F, Teich J Journal article Electronic System-Level Synthesis Methodologies (2009) Gerstlauer A, Haubelt C, Pimentel A, Stefanov T, Gajski D, Teich J Journal article A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors (2009) Dutta H, Kissler D, Hannig F, Kupriyanov O, Teich J, Pottier B Journal article Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis (2009) Dutta H, Hannig F, Teich J Conference contribution Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines (2009) Dutta H, Zhai J, Hannig F, Teich J Conference contribution System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance (2009) Lari V, Hannig F, Teich J Conference contribution Self-Organizing Multi-cue Fusion for FPGA-based Embedded Imaging (2009) Wildermann S, Walla G, Ziermann T, Teich J Conference contribution Self-Organizing Bandwidth Sharing in Priority-based Medium Access (2009) Wildermann S, Ziermann T, Teich J Conference contribution Run time Mapping of AdaptiveApplications onto Homogeneous NoC-based Reconfigurable Architectures (2009) Wildermann S, Ziermann T, Teich J Conference contribution