Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Symbolic system level reliability analysis (2010) Glaß M, Lukasiewycz M, Reimann F, Haubelt C, Teich J Conference contribution, Conference Contribution ReCoNets-design methodology for embedded systems consisting of small networks of reconfigurable nodes and connections (2010) Haubelt C, Koch D, Reimann F, Streichert T, Teich J Authored book, other Erlangen slot machine: An FPGA-based dynamically reconfigurable computing platform (2010) Angermeier J, Bobda C, Majer M, Teich J Authored book, other Efficient high-level modeling in the networking domain (2010) Zebelein C, Falk J, Haubelt C, Teich J, Dorsch R Conference contribution, Conference Contribution Efficient approximately-timed performance modeling for architectural exploration of MPSoCs (2010) Streubühr M, Gladigau J, Haubelt C, Teich J Authored book, Volume of book series Analysis of systemc actor networks for efficient synthesis (2010) Falk J, Zebelein C, Keinert J, Haubelt C, Teich J, Bhattacharyya SS Journal article, Original article Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications (2010) Platzner M, Teich J, Wehn N Authored book A self-organizing distributed reinforcement learning algorithm to achieve fair bandwidth allocation for priority-based bus communication (2010) Ziermann T, Mühleis N, Wildermann S, Teich J Conference contribution, Conference Contribution Echtzeitanalyse Ethernet-basierter E/E-Architekturen im Automobil (2010) Reimann F, Kern A, Haubelt C, Streichert T, Teich J Conference contribution A system-level synthesis approach from formal application models to generic bus-based MPSoCs (2010) Gladigau J, Gerstlauer A, Haubelt C, Streubühr M, Teich J Conference contribution, Conference Contribution