Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays (2011) Kissler D, Gran D, Salcic Z, Hannig F, Teich J Journal article A Co-Simulation Approach for Control Performance Analysis during Design Space Exploration of Cyber-Physical Systems (2011) Mühleis N, Glaß M, Zhang L, Teich J Conference contribution Stress-Aware Module Placement on Reconfigurable Devices (2011) Angermeier J, Ziener D, Glaß M, Teich J Conference contribution Automatic System-Level Synthesis: From Formal Application Models to Generic Bus-Based MPSoCs (2011) Gladigau J, Gerstlauer A, Haubelt C, Streubühr M, Teich J Journal article Integrated Modeling Using Finite State Machines and Dataflow Graphs (2010) Falk J, Keinert J, Haubelt C, Teich J, Zebelein C Book chapter / Article in edited volumes Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation (2010) Kiesel R, Löhlein O, Terzis A, Streubühr M, Haubelt C, Teich J Conference contribution Digitale Hardware/Software-Systeme: Spezifikation und Verifikation (2010) Haubelt C, Teich J Authored book New Directions for FPGA IP Core Watermarking and Identification (2010) Ziener D, Teich J Conference contribution Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models (2010) Falk J, Zebelein C, Haubelt C, Teich J, Dorsch R Conference contribution ReCoNodes-optimization methods for module scheduling and placement on reconfigurable hardware devices (2010) Ahmadinia A, Angermeier J, Fekete SP, Kamphans T, Koch D, Majer M, Schweer N, et al. Authored book, other