Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs (2012) Zebelein C, Falk J, Haubelt C, Teich J Conference contribution, Conference Contribution Model-Based Virtual Prototype Acceleration (2012) Gladigau J, Haubelt C, Teich J Journal article Symbolic System-level Design Methodology for Multi-Mode Reconfigurable Systems (2012) Wildermann S, Reimann F, Ziener D, Teich J Journal article Placing Multi-mode Streaming Applications on Dynamically Partially Reconfigurable Architectures (2012) Wildermann S, Angermeier J, Sibirko E, Teich J Journal article Dynamic Defragmentation of Reconfigurable Devices (2012) Fekete SP, Kamphans T, Schweer N, Tessars C, Van Der Veen JC, Angermeier J, Koch D, Teich J Journal article A very fast and quasi-accurate power-state-based system-level power modeling methodology (2012) Xu Y, Rosales R, Wang B, Streubühr M, Hasholzner R, Haubelt C, Teich J Conference contribution Mastering Software Variant Explosion for GPU Accelerators (2012) Membarth R, Hannig F, Teich J, Körner M, Eckert W Book chapter / Article in edited volumes Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes (2012) Graf S, Glaß M, Teich J Conference contribution System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems (2012) Wildermann S, Reimann F, Ziener D, Teich J Conference contribution System-Level Modeling and Simulation of Networked PROFINET IO Controllers (2012) Zhang L, Streubühr M, Glaß M, Teich J, von Schwerin A, Liu K Conference contribution