Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Techniques for on-demand structural redundancy for massively parallel processor arrays (2015) Teich J, Lari V, Tanase AP, Witterauf M, Khosravi F, Meyer B Journal article, Original article Quasi-static scheduling of data flow graphs in the presence of limited channel capacities (2015) Falk J, Schwarzer T, Glaß M, Teich J, Zebelein C, Haubelt C Conference contribution, Conference Contribution On-demand fault-tolerant loop processing on massively parallel processor arrays (2015) Tanase AP, Witterauf M, Teich J, Hannig F, Lari V Conference contribution, Conference Contribution Importance measures in time-dependent reliability analysis and system design (2015) Aliee H, Borgonovo E, Glaß M, Teich J Conference contribution, Conference Contribution Loop Coarsening in C-based High-Level Synthesis (2015) Schmid M, Reiche O, Hannig F, Teich J Conference contribution, Conference Contribution A Methodology for the Optimized Design of an E/E Architecture Component Platform (2015) Graf S, Glaß M, Teich J, Platte D Conference contribution Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays (2015) Tanase AP, Witterauf M, Hannig F, Teich J Conference contribution, Conference Contribution Resource-awareness on heterogeneous MPSoCs for image processing (2015) Paul J, Stechele W, Oechslein B, Erhardt C, Schedel J, Lohmann D, Schröder-Preikschat W, et al. Journal article, Original article Network interface with task spawning support for NoC-based DSM architectures (2015) Zaib A, Heißwolf J, Weichslgartner A, Wild T, Teich J, Becker J, Herkersdorf A Conference contribution Fault-tolerant communication in invasive networks on chip (2015) Heißwolf J, Weichslgartner A, Zaib A, Friederich S, Masing L, Stein C, Duden M, et al. Conference contribution, Conference Contribution