Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Loop Coarsening in C-based High-Level Synthesis (2015) Schmid M, Reiche O, Hannig F, Teich J Conference contribution, Conference Contribution A Methodology for the Optimized Design of an E/E Architecture Component Platform (2015) Graf S, Glaß M, Teich J, Platte D Conference contribution Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays (2015) Tanase AP, Witterauf M, Hannig F, Teich J Conference contribution, Conference Contribution Resource-awareness on heterogeneous MPSoCs for image processing (2015) Paul J, Stechele W, Oechslein B, Erhardt C, Schedel J, Lohmann D, Schröder-Preikschat W, et al. Journal article, Original article Network interface with task spawning support for NoC-based DSM architectures (2015) Zaib A, Heißwolf J, Weichslgartner A, Wild T, Teich J, Becker J, Herkersdorf A Conference contribution Fault-tolerant communication in invasive networks on chip (2015) Heißwolf J, Weichslgartner A, Zaib A, Friederich S, Masing L, Stein C, Duden M, et al. Conference contribution, Conference Contribution Design Methodology and Run-Time Management for Predictable Many-Core Systems (2015) Wildermann S, Weichslgartner A, Teich J Conference contribution, Conference Contribution Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms (2015) Gangadharan D, Sousa É, Lari V, Hannig F, Teich J Conference contribution, Conference Contribution Reliability of Space-Grade vs. COTS SRAM-Based FPGA in N-Modular Redundancy (2015) Glein R, Rittner F, Becher A, Ziener D, Frickel J, Teich J, Heuberger A Conference contribution, Conference Contribution Invasive computing for predictable stream processing: A simulation-based case study (2015) Roloff S, Wildermann S, Hannig F, Teich J Conference contribution, Conference Contribution