Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

FPGA-Based Accelerator Design from a Domain-Specific Language (2016) Özkan MA, Reiche O, Hannig F, Teich J Conference contribution FPGA-Based Dynamically Reconfigurable SQL Query Processing (2016) Ziener D, Weber H, Vogt JS, Schürfeld U, Meyer-Wegener K, Teich J, Dennl C, et al. Journal article Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge (2015) Reiche O, Häublein K, Reichenbach M, Schmid M, Hannig F, Teich J, Fey D Journal article Generation of Multigrid-based Numerical Solvers for FPGA Accelerators (2015) Schmitt C, Schmid M, Hannig F, Teich J, Kuckuk S, Köstler H Conference contribution Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing (2015) Witterauf M, Tanase AP, Hannig F, Teich J Conference contribution Bridging Algorithm and ESL Design: MATLAB/Simulink Model Transformation and Validation (2015) Zhang L, Glaß M, Ballmann N, Teich J Book chapter / Article in edited volumes Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays (2015) Teich J, Boppu S, Hannig F, Lari V Book chapter / Article in edited volumes Insights on the Configuration and Performances of SOME/IP Service Discovery (2015) Seyler J, Navet N, Fejoz L, Teich J Journal article FPGA-Based Dynamically Reconfigurable SQL Query Processing (2015) Ziener D, Bauer F, Becher A, Dennl C, Meyer-Wegener K, Schürfeld U, Teich J, et al. Journal article Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays (2015) Sousa É, Hannig F, Teich J, Schlichtmann U, Chen Q Conference contribution, Conference Contribution