Architecture and Compiler Design

A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays (2017) Sousa É, Tanase AP, Hannig F, Teich J Conference contribution Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates (2017) Witterauf M, Hannig F, Teich J Conference contribution, Conference Contribution Power Density-Aware Resource Management for Heterogeneous Tiled Multicores (2017) Khdr H, Pagani S, Rodrigues Sousa E, Lari V, Pathania A, Hannig F, Shafique M, et al. Journal article InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip (2016) Roloff S, Hannig F, Teich J Conference contribution ActorX10: An Actor Library for X10 (2016) Roloff S, Pöppl A, Schwarzer T, Wildermann S, Baader M, Glaß M, Hannig F, Teich J Conference contribution LoopInvader: A Compiler for Tightly Coupled Processor Arrays (2016) Tanase AP, Witterauf M, Sousa É, Lari V, Hannig F, Teich J Conference contribution Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs (2016) Fickenscher J, Reiche O, Schlumberger J, Hannig F, Teich J Conference contribution Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures (2015) Hannig F, Herkersdorf A Journal article, Editorial Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures (2015) Roloff S, Schafhauser D, Hannig F, Teich J Conference contribution, Conference Contribution A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays (2015) Lari V, Tanase AP, Teich J, Witterauf M, Khosravi F, Hannig F, Meyer B Conference contribution, Conference Contribution