Every clock counts – 41 Ghz wide-range integer-N clock divider
Wagner CW, Gläser G, Kell G, Del Galdo G (2021)
Publication Type: Conference contribution
Publication year: 2021
Publisher: VDE VERLAG GMBH
Pages Range: 388-391
Conference Proceedings Title: SMACD / PRIME 2021 - International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design and 16th Conference on PhD Research in Microelectronics and Electronics
Event location: Virtual, Online
ISBN: 9783800755899
Abstract
Current clock divider architectures suffer from either inflexible divider ranges or slow performance due to long logic paths. When implementing Compressed Sensing (CS) signal acquisition for systems operating at mm-wave Radio Frequency (RF), both flexibility and operation at the limits of the technology node are required. We propose a configurable integer-N clock divider architecture with synchronous reset that satisfies this need. With a wide divider range of S = 8. . . 1048583, an output duty cycle of 50 % is guaranteed for even, and approached for odd divider factors. The architecture is suited for operation with very high input clock frequencies, approaching the transit frequency of the technology. The key to construct our design is a serializer based approach, that enables the control logic to operate on two levels of lower frequencies. A symbol generator provides the output symbol stream. Internal clocks are derived directly from internal state vectors. In this way, the 20 bit divider range is achieved with only 22 Flip Flops (FFs) (excluding the serializer) and no combinatory logic in the fastest clock domain. We demonstrate our architecture in 130 nm SiGe BiCMOS technology using Positive Emitter Coupled Logic (PECL). We show that transistor-level simulation using calibrated fab models confirms successful operation up to f0 = 41.70 GHz which corresponds to ˜1/6th of the process transition frequency. At a die area of 0.06 mm2 (including serializer), our design draws ˜ 225 mW from a 2.50 V supply.
Involved external institutions
Technische Universität Ilmenau
Germany (DE)
Institut für Mikroelektronik - und Mechatronik-Systeme gemeinnützige GmbH (IMMS GmbH)
Germany (DE)
Technische Hochschule Brandenburg / Brandenburg University of Applied Sciences
Germany (DE)
Germany (DE)
Institut für Mikroelektronik - und Mechatronik-Systeme gemeinnützige GmbH (IMMS GmbH)
Germany (DE)
Technische Hochschule Brandenburg / Brandenburg University of Applied Sciences
Germany (DE)
How to cite
APA:
Wagner, C.W., Gläser, G., Kell, G., & Del Galdo, G. (2021). Every clock counts – 41 Ghz wide-range integer-N clock divider. In SMACD / PRIME 2021 - International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design and 16th Conference on PhD Research in Microelectronics and Electronics (pp. 388-391). Virtual, Online: VDE VERLAG GMBH.
MLA:
Wagner, Christoph W., et al. "Every clock counts – 41 Ghz wide-range integer-N clock divider." Proceedings of the 2021 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2021 and 16th Conference on PhD Research in Microelectronics and Electronics, PRIME 2021, Virtual, Online VDE VERLAG GMBH, 2021. 388-391.
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