Coding for Computation: Efficient Compression of Neural Networks for Reconfigurable Hardware
Rosenberger H, Fischer R, Fröhlich J, Bereyhi A, Müller R (2025)
Publication Type: Conference contribution
Publication year: 2025
Publisher: IEEE
City/Town: New York City
Pages Range: 1-5
Conference Proceedings Title: 2025 IEEE Statistical Signal Processing Workshop (SSP)
Event location: Edinburgh
DOI: 10.1109/SSP64130.2025.11073129
Abstract
As state of the art neural networks (NNs) continue to grow in size, their resource-efficient implementation becomes ever more important. In this paper, we introduce a compression scheme that reduces the number of computations required for NN inference on reconfigurable hardware such as FPGAs. This is achieved by combining pruning via regularized training, weight sharing and linear computation coding (LCC). Contrary to common NN compression techniques, where the objective is to reduce the memory used for storing the weights of the NNs, our approach is optimized to reduce the number of additions required for inference in a hardware-friendly manner. The proposed scheme achieves competitive performance for simple multilayer perceptrons, as well as for large scale deep NNs such as ResNet-34.
Authors with CRIS profile
Hans Rosenberger
Lehrstuhl für Digitale Übertragung (IDC)
Johanna Fröhlich
Professur für Informationsübertragung
Ralf Müller
Professur für Informationsübertragung
Involved external institutions
Germany (DE)
Canada (CA)How to cite
APA:
Rosenberger, H., Fischer, R., Fröhlich, J., Bereyhi, A., & Müller, R. (2025). Coding for Computation: Efficient Compression of Neural Networks for Reconfigurable Hardware. In 2025 IEEE Statistical Signal Processing Workshop (SSP) (pp. 1-5). Edinburgh, UA: New York City: IEEE.
MLA:
Rosenberger, Hans, et al. "Coding for Computation: Efficient Compression of Neural Networks for Reconfigurable Hardware." Proceedings of the 2025 IEEE Statistical Signal Processing Workshop (SSP), Edinburgh New York City: IEEE, 2025. 1-5.
BibTeX: Download