Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

Meinerzhagen P, Sherazi SM, Burg A, Rodrigues JN (2011)

Publication Type: Journal article

Publication year: 2011

Journal

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Institute of Electrical and Electronics Engineers (IEEE)

Book Volume: 1

Pages Range: 173-182

Article Number: 5976987

Journal Issue: 2

DOI: 10.1109/JETCAS.2011.2162159

Abstract

In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs. © 2011 IEEE.

Involved external institutions

École Polytechnique Fédérale de Lausanne (EPFL)

Switzerland (CH) Lund University / Lunds universitet

Sweden (SE)

How to cite

APA:

Meinerzhagen, P., Sherazi, S.M., Burg, A., & Rodrigues, J.N. (2011). Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 1(2), 173-182. https://doi.org/10.1109/JETCAS.2011.2162159

MLA:

Meinerzhagen, Pascal, et al. "Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1.2 (2011): 173-182.

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