Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

Sherazi SM, Nilsson P, Akgun OC, Sjoland H, Rodrigues JN (2011)

Publication Type: Conference contribution

Publication year: 2011

Journal

Proceedings - IEEE International Symposium on Circuits and Systems Institute of Electrical and Electronics Engineers

Pages Range: 837-840

Conference Proceedings Title: Proceedings - IEEE International Symposium on Circuits and Systems

Event location: BRA

ISBN: 9781424494736

DOI: 10.1109/ISCAS.2011.5937696

Abstract

This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results show that the low-leakage standard-threshold technology is suitable for the required throughput range between 250 Ksamples/s and 2Msamples/s, at a supply voltage of 260mV. The total energy dissipation of the filter is 205 fJ per sample. © 2011 IEEE.

Involved external institutions

Lund University / Lunds universitet

Sweden (SE)

How to cite

APA:

Sherazi, S.M., Nilsson, P., Akgun, O.C., Sjoland, H., & Rodrigues, J.N. (2011). Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 837-840). BRA.

MLA:

Sherazi, S. M.Yasser, et al. "Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain." Proceedings of the 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, BRA 2011. 837-840.

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