Ultra-low-power error correction circuits: Technology scaling and Sub-VT Operation

Winstead C, Rodrigues JN (2012)

Publication Type: Journal article

Publication year: 2012

Journal

IEEE Transactions on Circuits and Systems II: Express Briefs Institute of Electrical and Electronics Engineers (IEEE)

Book Volume: 59

Pages Range: 913-917

Article Number: 6412785

Journal Issue: 12

DOI: 10.1109/TCSII.2012.2231040

Abstract

Techniques are evaluated for implementing error correction codes in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-V T analog decoding techniques. Novel sub-VT digital designs are proposed, and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub-VT implementation is predicted to offer 29× gain in power consumption for a (3,6) low-density parity-check decoder of length N = 512 operating at a throughput of 200 Mb/s, compared to standard digital implementation of the same design. © 2004-2012 IEEE.

Involved external institutions

Lund University / Lunds universitet

Sweden (SE)

How to cite

APA:

Winstead, C., & Rodrigues, J.N. (2012). Ultra-low-power error correction circuits: Technology scaling and Sub-VT Operation. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12), 913-917. https://doi.org/10.1109/TCSII.2012.2231040

MLA:

Winstead, Chris, and Joachim Neves Rodrigues. "Ultra-low-power error correction circuits: Technology scaling and Sub-VT Operation." IEEE Transactions on Circuits and Systems II: Express Briefs 59.12 (2012): 913-917.

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