Sizing of dual-VT gates for sub-VT circuits

Mohammadi B, Sherazi SM, Rodrigues JN (2012)

Publication Type: Conference contribution

Publication year: 2012

Conference Proceedings Title: 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012

Event location: USA

ISBN: 9781467315876

DOI: 10.1109/SubVT.2012.6404305

Abstract

This paper presents a novel method to improve the performance of sub-threshold (sub-VT) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively. © 2012 IEEE.

Involved external institutions

Lund University / Lunds universitet SE Sweden (SE)

How to cite

APA:

Mohammadi, B., Sherazi, S.M., & Rodrigues, J.N. (2012). Sizing of dual-VT gates for sub-VT circuits. In 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012. USA.

MLA:

Mohammadi, Babak, S. M.Yasser Sherazi, and Joachim Neves Rodrigues. "Sizing of dual-VT gates for sub-VT circuits." Proceedings of the 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012, USA 2012.

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