Sub-VT design of a wake-up receiver back-end in 65 nm CMOS
Mazloum NS, Rodrigues JN, Edfors O (2012)
Publication Type: Conference contribution
Publication year: 2012
Conference Proceedings Title: 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012
Event location: USA
ISBN: 9781467315876
DOI: 10.1109/SubVT.2012.6404304
Abstract
In sensor network applications, the use of duty-cycled ultra-low power wake-up receivers can significantly reduce overall power consumption. An important complement to previous investigations is to show that low-power wake-up receivers with good enough detection performance can be realized in hardware. In this paper we address this very issue by presenting the design, implementation, and sub-VT characterization of a digital back-end for such an ultra-low power WRx. © 2012 IEEE.
Involved external institutions
Sweden (SE)How to cite
APA:
Mazloum, N.S., Rodrigues, J.N., & Edfors, O. (2012). Sub-VT design of a wake-up receiver back-end in 65 nm CMOS. In 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012. USA.
MLA:
Mazloum, Nafiseh Seyed, Joachim Neves Rodrigues, and Ove Edfors. "Sub-VT design of a wake-up receiver back-end in 65 nm CMOS." Proceedings of the 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012, USA 2012.
BibTeX: Download