A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs

Muller C, Malkowsky S, Andersson O, Mohammadi B, Sparso J, Rodrigues JN (2013)

Publication Type: Conference contribution

Publication year: 2013

Publisher: IEEE Computer Society

Pages Range: 380-385

Conference Proceedings Title: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

Event location: TUR

ISBN: 9781479905249

DOI: 10.1109/VLSI-SoC.2013.6673313

Abstract

This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-VT regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach. © 2013 IEEE.

Involved external institutions

Lund University / Lunds universitet SE Sweden (SE) Technical University of Denmark / Danmarks Tekniske Universitet (DTU) DK Denmark (DK)

How to cite

APA:

Muller, C., Malkowsky, S., Andersson, O., Mohammadi, B., Sparso, J., & Rodrigues, J.N. (2013). A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. In IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC (pp. 380-385). TUR: IEEE Computer Society.

MLA:

Muller, Christoph, et al. "A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs." Proceedings of the 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013, TUR IEEE Computer Society, 2013. 380-385.

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