A 0.28¿0.8V 320 fW D-latch for sub-VT memories in 65 nm CMOS

Mohammadi B, Andersson O, Meinerzhagen P, Sherazi Y, Burg A, Rodrigues JN (2014)

Publication Type: Conference contribution

Publication year: 2014

Publisher: IEEE Computer Society

Conference Proceedings Title: 2014 IEEE Faible Tension Faible Consommation, FTFC 2014

Event location: MCO

ISBN: 9781479937738

DOI: 10.1109/FTFC.2014.6828618

Abstract

The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power. © 2014 IEEE.

Involved external institutions

Lund University / Lunds universitet

Sweden (SE) École Polytechnique Fédérale de Lausanne (EPFL)

Switzerland (CH)

How to cite

APA:

Mohammadi, B., Andersson, O., Meinerzhagen, P., Sherazi, Y., Burg, A., & Rodrigues, J.N. (2014). A 0.28¿0.8V 320 fW D-latch for sub-VT memories in 65 nm CMOS. In 2014 IEEE Faible Tension Faible Consommation, FTFC 2014. MCO: IEEE Computer Society.

MLA:

Mohammadi, Babak, et al. "A 0.28¿0.8V 320 fW D-latch for sub-VT memories in 65 nm CMOS." Proceedings of the 2014 IEEE Faible Tension Faible Consommation, FTFC 2014, MCO IEEE Computer Society, 2014.

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