A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI

Mohammadi B, Andersson O, Nguyen J, Ciampolini L, Cathelin A, Rodrigues JN (2016)

Publication Type: Conference contribution

Publication year: 2016

Publisher: IEEE Computer Society

Book Volume: 2016-October

Pages Range: 429-432

Conference Proceedings Title: European Solid-State Circuits Conference

Event location: Lausanne, CHE

ISBN: 9781509029723

DOI: 10.1109/ESSCIRC.2016.7598333

Abstract

In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240mV and the retention voltage is found at 200mV.

Involved external institutions

Lund University / Lunds universitet SE Sweden (SE) STMicroelectronics (France) FR France (FR)

How to cite

APA:

Mohammadi, B., Andersson, O., Nguyen, J., Ciampolini, L., Cathelin, A., & Rodrigues, J.N. (2016). A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI. In European Solid-State Circuits Conference (pp. 429-432). Lausanne, CHE: IEEE Computer Society.

MLA:

Mohammadi, Babak, et al. "A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI." Proceedings of the 42nd European Solid-State Circuits Conference, ESSCIRC 2016, Lausanne, CHE IEEE Computer Society, 2016. 429-432.

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