Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory

Hosseinzadeh S, Lancaster S, Parvaresh A, Silva C, Fey D (2024)

Publication Type: Conference contribution

Publication year: 2024

Publisher: Institute of Electrical and Electronics Engineers Inc.

Pages Range: 1-10

Conference Proceedings Title: Proceedings - 2024 27th Euromicro Conference on Digital System Design, DSD 2024

Event location: Paris FR

ISBN: 9798350380385

DOI: 10.1109/DSD64264.2024.00010

Abstract

This paper explores CMOS-compatible Ferroelectric Tunnel Junctions (FTJs) for Processing-In-Memory (PIM) to address the 'memory wall' in traditional computing. A novel FTJ noise model was developed, and hardware-calibrated devices were modeled utilizing IBM's Analog In-Memory Hardware Acceleration Toolkit (AIHWKit). We simulate FTJ-based neural networks for inference only, focusing on mitigating non-idealities such as conductance drift, programming noise, and 1/f read noise. To mitigate FTJ non-idealities affecting different neural networks' accuracy, we developed various hardware-aware (HWA) training techniques including, but not limited to, different weight redistribution, noise resiliency, and custom activation functions. Exploiting the hardware-aware techniques used in this paper, considering different weight-to-conductance mapping and conductance and weight range enlargement, depicts an accuracy improvement in three case studies: full adder implementation, MNIST and CIFAR-10 benchmark, with best-case scenario accuracy of 96.96 %, 86.92 %, and 86.36 %, respectively, after four months of inference. Furthermore, scalability, accuracy im-provement, and experimental validation confirm FTJs' potential for Processing-in-Memory, providing valuable insights for future device and circuit design optimizations to enhance performance and reliability.

Authors with CRIS profile

Shima Hosseinzadeh Foroushani Lehrstuhl für Informatik 3 (Rechnerarchitektur) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Involved external institutions

NaMLab gGmbH DE Germany (DE)

How to cite

APA:

Hosseinzadeh, S., Lancaster, S., Parvaresh, A., Silva, C., & Fey, D. (2024). Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory. In Tomasz Kryjak, Frederic Petrot (Eds.), Proceedings - 2024 27th Euromicro Conference on Digital System Design, DSD 2024 (pp. 1-10). Paris, FR: Institute of Electrical and Electronics Engineers Inc..

MLA:

Hosseinzadeh, Shima, et al. "Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory." Proceedings of the 27th Euromicro Conference on Digital System Design, DSD 2024, Paris Ed. Tomasz Kryjak, Frederic Petrot, Institute of Electrical and Electronics Engineers Inc., 2024. 1-10.

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