In-Memory Implementation of an Approximate Adder With Reduced Latency and Error
Lakshmi V, Pudi V, Reuben JR (2024)
Publication Type: Journal article
Publication year: 2024
Journal
DOI: 10.1109/TCSI.2024.3511955
Abstract
In-memory computing has been a prominent solution to Von Neumann bottleneck that degrades the performance of a computing system. Approximate computing is widely used to improve the performance of multimedia and other applications that are error-tolerant. Approximate adders being the basic units used to design other complex units, get benefited when implemented in-memory by taking the advantages of both in-memory computing and approximate computing. In this work, we have improved the speculative carry select adder to minimize error and critical path delay by eliminating multiplexers. The proposed adder achieves less critical path, area, improved error characteristics such as error rate, normalized mean error distance and mean relative error distance when compared to the state-of-the-art approximate adders. Error rate of the proposed adder is 34.48% less than the best reported 32-bit adder with sub-adder size of 8-bit. When the proposed approximate adders are implemented in-memory using majority logic, they achieve better performance compared to the existing in-memory approximate adders. Latency of the proposed adders is observed to be a constant irrespective of adder size for a fixed sub-adder size.
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India (IN)How to cite
APA:
Lakshmi, V., Pudi, V., & Reuben, J.R. (2024). In-Memory Implementation of an Approximate Adder With Reduced Latency and Error. IEEE Transactions on Circuits and Systems I-Regular Papers. https://doi.org/10.1109/TCSI.2024.3511955
MLA:
Lakshmi, Vijaya, Vikramkumar Pudi, and John Reuben Reuben. "In-Memory Implementation of an Approximate Adder With Reduced Latency and Error." IEEE Transactions on Circuits and Systems I-Regular Papers (2024).
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