Ebrahimiazandaryani F, Fey D (2024)
Publication Language: English
Publication Type: Journal article
Publication year: 2024
Book Volume: 107
Article Number: 105058
DOI: 10.1016/j.micpro.2024.105058
This paper presents an effective μ-architectural design method, called ExTern, to enhance the performance of a RISC-V processor experiencing computation bottlenecks. ExTern involves integrating Canonical Signed Digit (CSD) representation, a ternary number system enabling carry/borrow-free addition/subtraction in constant time O(1), into the RISC-V processor, particularly into the execution stage. Furthermore, it adopts an extended six-stage pipeline architecture to maximize employed encoding benefits, leading to more improvement in overall execution time and throughput. Despite the presence of optimized circuits, such as fast carry chain (CARRY4) modules for binary encoding on FPGA, the customized processor applying ExTern, RISC-VT, showcases remarkable improvement in computation performance. Experimental results demonstrate a 34.3% (12.2%) improvement in working frequency leading to a lower 31% (11.5%) execution time and a 32% (12%) increase in throughput compared to a State-of-the-Art open-source five(six)-stage RISC-V processor.
APA:
Ebrahimiazandaryani, F., & Fey, D. (2024). ExTern: Boosting RISC-V core performance using ternary encoding. Microprocessors and Microsystems, 107. https://doi.org/10.1016/j.micpro.2024.105058
MLA:
Ebrahimiazandaryani, Farhad, and Dietmar Fey. "ExTern: Boosting RISC-V core performance using ternary encoding." Microprocessors and Microsystems 107 (2024).
BibTeX: Download