Fault-Tolerant Parity Readout on a Shuttling-Based Trapped-Ion Quantum Computer

Hilder J, Pijn D, Onishchenko O, Stahl A, Orth M, Lekitsch B, Rodriguez-Blanco A, Mueller M, Schmidt-Kaler F, Poschinger UG (2022)

Publication Type: Journal article

Publication year: 2022

Journal

Physical Review X American Physical Society

Book Volume: 12

Article Number: 011032

Journal Issue: 1

DOI: 10.1103/PhysRevX.12.011032

Abstract

Quantum error correction requires the detection of errors via reliable measurements of multiqubit correlation operators. As these operations are inherently faulty, fault-tolerant schemes for realizing quantum error correction are required. Recently, a paradigm requiring only minimal resource overhead in the form of "flag"qubits to detect and correct errors has been proposed. We experimentally demonstrate a fault-tolerant weight-4 parity-check measurement scheme, where one additional flag qubit serves to detect errors, which would otherwise proliferate into uncorrectable weight-2 errors onto the qubit register. We achieve a parity measurement fidelity of 92.3(2)%, which increases to 93.2(2)% upon conditioning to the flag readout result, which shows that the measurement scheme intercepts intrinsic errors occurring throughout the sequence. We show that the protocol is capable of reliably intercepting faults by deliberately injecting bit- and phase-flip errors. For holistic benchmarking of the parity measurement scheme, we use an entanglement witnessing scheme requiring a minimal number of measurements to verify genuine six-qubit multipartite entanglement. The demonstrated fault-tolerant parity measurement scheme constitutes the key building block in a broad class of resource-efficient flag-based quantum error correction protocols including topological color codes. Our hardware platform is based on atomic ions stored in a microchip ion trap. The qubit register is dynamically reconfigured via shuttling operations enabling effective full connectivity without operational cross talk, thereby providing key prerequisites underlying fault-tolerant circuit design. These architectural features in combination with the demonstrated approach to flag-based fault-tolerant quantum error correction open up a route toward scalable fault-tolerant quantum computing.

Involved external institutions

Johannes Gutenberg-Universität Mainz (JGU) DE Germany (DE) Universidad Complutense de Madrid (UCM) ES Spain (ES) Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen DE Germany (DE)

How to cite

APA:

Hilder, J., Pijn, D., Onishchenko, O., Stahl, A., Orth, M., Lekitsch, B.,... Poschinger, U.G. (2022). Fault-Tolerant Parity Readout on a Shuttling-Based Trapped-Ion Quantum Computer. Physical Review X, 12(1). https://dx.doi.org/10.1103/PhysRevX.12.011032

MLA:

Hilder, Janine, et al. "Fault-Tolerant Parity Readout on a Shuttling-Based Trapped-Ion Quantum Computer." Physical Review X 12.1 (2022).

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