Pregl S, Heinzig A, Baraban L, Cuniberti G, Mikolajick T, Weber WM (2016)
Publication Type: Journal article
Publication year: 2016
Book Volume: 15
Pages Range: 549-556
Article Number: 7452632
Journal Issue: 3
DOI: 10.1109/TNANO.2016.2542525
In this paper, we present a novel technology of printable bottom-up grown Si nanowire parallel arrays for low-dissipation power electronics. Parallel aligned layers of monocrystalline Si nanowires can be deposited on arbitrary substrates over large areas by the printing process. The presented transistors consist of parallel arrays of longitudinal NiSi
APA:
Pregl, S., Heinzig, A., Baraban, L., Cuniberti, G., Mikolajick, T., & Weber, W.M. (2016). Printable parallel arrays of Si nanowire schottky-barrier-FETs with tunable polarity for complementary logic. IEEE Transactions on Nanotechnology, 15(3), 549-556. https://doi.org/10.1109/TNANO.2016.2542525
MLA:
Pregl, Sebastian, et al. "Printable parallel arrays of Si nanowire schottky-barrier-FETs with tunable polarity for complementary logic." IEEE Transactions on Nanotechnology 15.3 (2016): 549-556.
BibTeX: Download