A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows
Pechmann S, Hagelauer A (2022)
Publication Type: Conference contribution
Publication year: 2022
Journal
Publisher: Institute of Electrical and Electronics Engineers Inc.
Book Volume: 2022-August
Conference Proceedings Title: Midwest Symposium on Circuits and Systems
Event location: Fukuoka, JPN
ISBN: 9781665402798
DOI: 10.1109/MWSCAS54063.2022.9859436
Abstract
Memory integration is a key issue for emerging memory technologies. In order to properly integrate a novel memory technology, precise and reliable read circuits and concepts are necessary. But especially in emerging technologies, the electrical properties of the individual cells can vary widely, demanding additional flexibility. The presented circuit design offers a read circuit for RRAM cells based on voltage evaluation, that is able to resolve very small resistance ratios of up to 1.31 while offering multi-level capability. By changing some circuit parameters, it can be adopted to different given electrical properties.
Involved external institutions
Germany (DE)How to cite
APA:
Pechmann, S., & Hagelauer, A. (2022). A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows. In Midwest Symposium on Circuits and Systems. Fukuoka, JPN: Institute of Electrical and Electronics Engineers Inc..
MLA:
Pechmann, Stefan, and Amelie Hagelauer. "A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows." Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022, Fukuoka, JPN Institute of Electrical and Electronics Engineers Inc., 2022.
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