Alt C, Opdenhövel JO, Plessl C, Kenter T, Hönig J, Köstler H (2022)
Publication Type: Conference contribution, Abstract of a poster
Publication year: 2022
Event location: Hamburg
FPGAs are a promising hardware architecture for acceleration of various applications.
To run Shallow Water simulations on FPGAs, we present a code generation pipeline.
It starts from the existing implementation of a quadrature-free Discontinuous Galerkin
discretization of the Shallow Water Equation in GHODDESS.
For stencil generation we use pystencils with a custom backend and
target StencilStream, an FPGA library that is implemented on top of the Intel oneAPI.
While the code generation provides a stencil transition function with
multiple dependent stages, the StencilStream library contains an
FPGA-specific architecture template that allows to automatically overlap
and -- if FPGA resource constraints permit -- replicate the computation
stages.
The simulation is ultimately synthesized for and executed on FPGA hardware.
We show that the pipeline works for complex examples, by generating
applications with up to 3500 lines of code.
For small examples the performance is promising as the generated applications perform up to 3x faster than the CPU reference,
depending on the degree of replication achieved.
APA:
Alt, C., Opdenhövel, J.-O., Plessl, C., Kenter, T., Hönig, J., & Köstler, H. (2022, May). Bringing Water to the Fields - A Code Generation Pipeline for SWE Simulations on FPGAs. Poster presentation at ISC High Performance 2022, Hamburg.
MLA:
Alt, Christoph, et al. "Bringing Water to the Fields - A Code Generation Pipeline for SWE Simulations on FPGAs." Presented at ISC High Performance 2022, Hamburg 2022.
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