Si tunneling field effect transistor with tunnelling in-line with the gate field
Fischer IA, Hähnel D, Isemann H, Kottantharayil A, Murali G, Oehme M, Schulze J (2012)
Publication Type: Conference contribution
Publication year: 2012
Pages Range: 176-177
Conference Proceedings Title: 2012 International Silicon-Germanium Technology and Device Meeting, ISTDM 2012 - Proceedings
Event location: USA
ISBN: 9781457718625
DOI: 10.1109/ISTDM.2012.6222411
Abstract
The tunneling field effect transistor (TFET) is a device concept that has the potential to outperform CMOS technology both in energy efficiency and speed. One of the challenges for this device concept is to improve on-currents to meet industry standards. In order to attain this goal, a number of modifications to the basic design, concerning both material as well as geometry variations, have been proposed and evaluated in simulations. We report on the fabrication and performance of a Silicon TFET where an additional U-groove etching and molecular beam epitaxy (MBE) step are used to fabricate a device geometry where tunneling occurs in-line with the gate field. On the one hand, this enlarges the tunneling region, on the other hand it allows for atomically sharp doping transitions. First performance results are shown. © 2012 IEEE.
Involved external institutions
Germany (DE)
India (IN)How to cite
APA:
Fischer, I.A., Hähnel, D., Isemann, H., Kottantharayil, A., Murali, G., Oehme, M., & Schulze, J. (2012). Si tunneling field effect transistor with tunnelling in-line with the gate field. In 2012 International Silicon-Germanium Technology and Device Meeting, ISTDM 2012 - Proceedings (pp. 176-177). USA.
MLA:
Fischer, I. A., et al. "Si tunneling field effect transistor with tunnelling in-line with the gate field." Proceedings of the 6th International Silicon-Germanium Technology and Device Meeting, ISTDM 2012, USA 2012. 176-177.
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