Silicon tunneling field-effect transistors with tunneling in line with the gate field

Fischer IA, Bakibillah ASM, Golve M, Haehnel D, Isemann H, Kottantharayil A, Oehme M, Schulze J (2013)

Publication Type: Journal article

Publication year: 2013

Journal

IEEE Electron Device Letters Institute of Electrical and Electronics Engineers (IEEE)

Book Volume: 34

Pages Range: 154-156

Article Number: 6392851

Journal Issue: 2

DOI: 10.1109/LED.2012.2228250

Abstract

We present experimental results on the fabrication and characterization of vertical Si tunneling field-effect transistors (TFETs) in a device geometry with tunneling in line with the gate field. Compared to vertical Si TFETs without this geometry modification, on-currents are increased by more than one order of magnitude with ION =1.1μAμm at VDS = 0.5V and an IONIOFF ratio of 3.4 104 in n-channel operation. We present further suggestions for device improvements. © 1980-2012 IEEE.

Authors with CRIS profile

Jörg Schulze

Involved external institutions

Universität Stuttgart DE Germany (DE) Indian Institute of Technology Bombay IN India (IN)

How to cite

APA:

Fischer, I.A., Bakibillah, A.S.M., Golve, M., Haehnel, D., Isemann, H., Kottantharayil, A.,... Schulze, J. (2013). Silicon tunneling field-effect transistors with tunneling in line with the gate field. IEEE Electron Device Letters, 34(2), 154-156. https://doi.org/10.1109/LED.2012.2228250

MLA:

Fischer, Inga A., et al. "Silicon tunneling field-effect transistors with tunneling in line with the gate field." IEEE Electron Device Letters 34.2 (2013): 154-156.

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