Das B, Meshram R, Ostwal V, Schulze J, Ganguly U (2014)
Publication Type: Conference contribution
Publication year: 2014
Publisher: Institute of Electrical and Electronics Engineers Inc.
Pages Range: 139-140
Conference Proceedings Title: Device Research Conference - Conference Digest, DRC
Event location: USA
ISBN: 9781479954056
Low voltage impact ionization (II) has been proposed for various devices in logic (e.g. IMOS [1]) for steep sub-threshold swing (SS<60mV/decade) and memory (e.g. I-NPN selector [2], biristor [3, 4], ZRAM [5]) for both steep SS (<60mV/decade) and charge storage for DRAM/SRAM replacement. Recently, we have proposed a synapse device based on I-NPN for neuro-morphic computing [6]. Various simulations studies have shown low bias, high SS device performance-which makes II based devices promising [2]. However, while steep SS has been demonstrated at high bias across the junctions (or S/D bias for MOSFETs), a critical challenge has been the demonstration of sub-1V (Table 1). In this paper, we demonstrate for the first time impact ionization at sub-0.5V in a dopant profile engineered NPN device which produces steeper turn on that thermal activation limit. © 2014 IEEE.
APA:
Das, B., Meshram, R., Ostwal, V., Schulze, J., & Ganguly, U. (2014). Observation of impact ionization at sub-0.5V and resultant improvement in ideality in I-NPN selector device by Si epitaxy for RRAM applications. In Device Research Conference - Conference Digest, DRC (pp. 139-140). USA: Institute of Electrical and Electronics Engineers Inc..
MLA:
Das, B., et al. "Observation of impact ionization at sub-0.5V and resultant improvement in ideality in I-NPN selector device by Si epitaxy for RRAM applications." Proceedings of the 72nd Device Research Conference, DRC 2014, USA Institute of Electrical and Electronics Engineers Inc., 2014. 139-140.
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