Fabrication and simulation of vertical Ge-based P-channel planar-doped barrier FETs with 40 nm channel length

Elogail Y, Elkhouly K, Fischer I, Kostecki K, Schulze J (2017)

Publication Type: Conference contribution

Publication year: 2017

Publisher: Institute of Electrical and Electronics Engineers Inc.

Book Volume: 2018-January

Pages Range: 1-3

Conference Proceedings Title: 2017 5th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2017 - Proceedings

Event location: Berkeley, CA US

ISBN: 9781538632901

DOI: 10.1109/E3S.2017.8246166

Abstract

Ge integrated on Si is a promising candidate for energy-efficient field effect transistor (FET) applications due to its high mobility and compatibility to CMOS technology. Nevertheless, using Ge in FET fabrication is challenging due to difficulties in controlling the transistor channel/gate oxide interface properties and suppressing crystal defects such as threading dislocations that arise from Ge integration on Si. Furthermore, the smaller bandgap of Ge compared to Si can give rise to higher band-To-band tunneling leakage currents [1-2]. All these challenges severely affect the on-state (Ion) and off-state (Ioff) currents. With respect to simulation, the majority of the physical models parameters are calibrated for Si. For Ge, the parameters are still less well known. In this work, we present the fabrication and characterization of vertical Ge-based p-channel Planar-Doped Barrier FETs (p-PDBFETs). Our experimental results are then used to calibrate our simulation model. Based on simulation data, an improved transistor design is proposed.

Authors with CRIS profile

Jörg Schulze

Involved external institutions

German University in Cairo (GUC) / الجامعة الألمانية بالقاهرة EG Egypt (EG) Universität Stuttgart DE Germany (DE)

How to cite

APA:

Elogail, Y., Elkhouly, K., Fischer, I., Kostecki, K., & Schulze, J. (2017). Fabrication and simulation of vertical Ge-based P-channel planar-doped barrier FETs with 40 nm channel length. In 2017 5th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2017 - Proceedings (pp. 1-3). Berkeley, CA, US: Institute of Electrical and Electronics Engineers Inc..

MLA:

Elogail, Yasmine, et al. "Fabrication and simulation of vertical Ge-based P-channel planar-doped barrier FETs with 40 nm channel length." Proceedings of the 5th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2017, Berkeley, CA Institute of Electrical and Electronics Engineers Inc., 2017. 1-3.

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