Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge1-x-ySn y heterostructure model for low power FET applications

Elogail Y, Fischer IA, Wendav T, Schulze J (2018)

Publication Type: Journal article

Publication year: 2018

Journal

Semiconductor Science and Technology Institute of Physics: Hybrid Open Access

Book Volume: 33

Article Number: 114001

Journal Issue: 11

DOI: 10.1088/1361-6641/aae001

Abstract

High mobility materials are being studied to replace Si with the aim of enhancing the performance of nanoelectronic devices. Ge and III-V channels have recently received a lot of attention, where the combination of III-V channels in n-MOSFETs and Ge channels in p-MOSFETs integrated on Si substrates is regarded as a promising CMOS design. Ge integrated on Si is a very promising choice due to its superior transport properties and compatibility to CMOS technology. The main challenges faced by Ge-based FETs are the channel/gate interface quality, crystal defects due to integration on Si and the smaller bandgap compared to Si, which leads to elevated band-to-band-tunnelling leakage currents, setting limitations on the achievable off state current (I OFF). In this work, we present results on the fabrication and characterization of vertical Ge-based p-channel planar doped barrier FET together with a simulation model based on extracted material data from our experimental work and literature. Based on the model, a design of a modified device using both planar doping and a heterostructure in the channel is presented. The channel engineered design uses a Ge/Si x Ge1-x-ySn y heterostructure, which is lattice matched to Ge, within the channel at different positions. The results show improved performance; the larger bandgap of the ternary alloy Si x Ge1-x-ySn y compared to Ge leads to a suppression of the I OFF as well as a reduced subthreshold swing, making the heterostructure device promising for energy efficient FET applications.

Authors with CRIS profile

Jörg Schulze

Involved external institutions

Universität Stuttgart DE Germany (DE) Humboldt-Universität zu Berlin DE Germany (DE)

How to cite

APA:

Elogail, Y., Fischer, I.A., Wendav, T., & Schulze, J. (2018). Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge1-x-ySn y heterostructure model for low power FET applications. Semiconductor Science and Technology, 33(11). https://doi.org/10.1088/1361-6641/aae001

MLA:

Elogail, Yasmine, et al. "Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge1-x-ySn y heterostructure model for low power FET applications." Semiconductor Science and Technology 33.11 (2018).

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