High speed low power phase accumulators for DDS applications in SiGe bipolar technology

Lämmle B, Wagner C, Knapp H, Maurer L, Weigel R (2009)

Publication Type: Conference contribution

Publication year: 2009

Pages Range: 162-165

Conference Proceedings Title: Bipolar/BiCMOS Circuits and Technology Meeting, 2009. BCTM 2009. IEEE

Event location: Capri, Italy

DOI: 10.1109/BIPOL.2009.5314253

Abstract

Two phase accumulators with 10 and 8 bit resolution, 7 and 15 GHz maximum clock rate, and a power consumption of 237 and 302.5 mW for use in direct digital synthesizers are presented. The accumulators are designed to retain phase coherency when a frequency switch is performed and are integrated into a DDS to perform simple measurement. The architecture is described, the circuits analyzed and measurements given. The chips are fabricated in a 0.35 mum 200-GHz fT SiGe bipolar technology and occupy only 1028 times 1128 mum2.

Authors with CRIS profile

Benjamin Lämmle Lehrstuhl für Technische Elektronik Robert Weigel Lehrstuhl für Technische Elektronik

Involved external institutions

Universität der Bundeswehr München DE Germany (DE)

How to cite

APA:

Lämmle, B., Wagner, C., Knapp, H., Maurer, L., & Weigel, R. (2009). High speed low power phase accumulators for DDS applications in SiGe bipolar technology. In Bipolar/BiCMOS Circuits and Technology Meeting, 2009. BCTM 2009. IEEE (pp. 162-165). Capri, Italy.

MLA:

Lämmle, Benjamin, et al. "High speed low power phase accumulators for DDS applications in SiGe bipolar technology." Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2009. BCTM 2009. IEEE, Capri, Italy 2009. 162-165.

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