Abd El-Azeem RS, El-Moursy MA, Nassar AM, Radwan A, Abou-El-Kheir NT, El-Kharashi MS (2016)
Publication Type: Journal article
Publication year: 2016
Publisher: Elsevier
Book Volume: 51
Pages Range: 112-118
DOI: 10.1016/j.mejo.2016.01.006
A Computational Filter (CF) that employs a sample calculation functional block is presented. CF significantly reduces the hardware requirements to realize an interpolation filter2. The Computational Filter is compared with advanced Finite Impulse Response (CFIR). CFIR programmable filter is implemented using a Computation Sharing Multiplication (CSHM) technique to optimize the conventional design. The proposed CF significantly reduces the implementation area as compared to CFIR. The maximum average error for wide range of interpolation factors from 8 to 256 is 2.59\% for CF and 0.02\% for CFIR. Xilinx Virtex5 FPGA XC5VTX240T device is used to compare the proposed design and the advanced CFIR for interpolation factor of 8, 16, 32, and 64. The Computational Filter average reduction in hardware implementation is 78.8\%, 89.5\%, 94.5\%, and 97.1\% for interpolation factor of 8, 16, 32, and 64, respectively. The maximum operating frequency for the CFIR is 1 MHz. The maximum operating frequency is 0.92 MHz, 0.57 MHz, 0.32 MHz, and 0.2 MHz for interpolation factor of 8, 16, 32, and 64, respectively.
APA:
Abd El-Azeem, R.S., El-Moursy, M.A., Nassar, A.M., Radwan, A., Abou-El-Kheir, N.T., & El-Kharashi, M.S. (2016). Direct computation for high performance interpolation filter. Microelectronics Journal, 51, 112-118. https://dx.doi.org/10.1016/j.mejo.2016.01.006
MLA:
Abd El-Azeem, Ratshih S., et al. "Direct computation for high performance interpolation filter." Microelectronics Journal 51 (2016): 112-118.
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