Münker C, Weigel R (2007)
Publication Type: Conference contribution
Publication year: 2007
Pages Range: 476-479
Conference Proceedings Title: 33rd European Solid State Circuits Conference ESSCIRC
Event location: Munich, Germany
DOI: 10.1109/ESSCIRC.2007.4430345
A built-in self test (BIST) solution for the on-chip spectral verification of a 4 GHz phase-locked loop (PLL) is presented. The PLL is embedded in an integrated cellular RF transceiver in a 130 nm CMOS technology. The BIST blocks enable the detection of catastrophic and many parametric faults by measuring the PLL frequency response and checking for spurious sidebands and excessive in-band phase noise without external test equipment. Multi-tone stimuli with a spurious-free dynamic range (SFDR) of 60 dB are generated on-chip, the PLL RF response is demodulated and digitized in an on-chip digital FM discriminator. Spectral analysis is performed using digital narrowband filtering, achieving an SFDR of 45 dB. The fully digital BIST blocks require a chip area of only 0.06 mm2 and do not compromise the performance of the PLL itself.
APA:
Münker, C., & Weigel, R. (2007). Spectral PLL built-in self-test for integrated cellular transceivers. In 33rd European Solid State Circuits Conference ESSCIRC (pp. 476-479). Munich, Germany.
MLA:
Münker, Christian, and Robert Weigel. "Spectral PLL built-in self-test for integrated cellular transceivers." Proceedings of the 33rd European Solid State Circuits Conference ESSCIRC, Munich, Germany 2007. 476-479.
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