A CMOS quad-band-sigma-delta-transceiver for GSM-EDGE with dual mode transmitter architecture for low noise and high linearity
Simon M, Weigel R, Neurauter B, Märzinger G (2004)
Publication Type: Conference contribution
Publication year: 2004
Pages Range: 431-434
Conference Proceedings Title: Radio Frequency Integrated Circuits (RFIC) Symposium
Event location: Fort Worth, Texas
DOI: 10.1109/RFIC.2004.1320644
Abstract
A 120 nm CMOS quad-band transceiver for GSM EDGE with a dual mode transmitter architecture and a constant gain direct conversion receiver has been developed. In GMSK mode, a direct conversion transmitter with third order ΣΔ-modulation loop modulates the phase of the VCO. The output signal is amplified by a low noise power efficient limiting output buffer with 6 dBm output power. A high linearity vector modulator is switched on to process the 8-PSK modulated EDGE signal with additional amplitude modulation. Neither TX-SAW nor third harmonic filter are needed for system integration into a handset to fulfil the GSM-EDGE specification.
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Austria (AT)How to cite
APA:
Simon, M., Weigel, R., Neurauter, B., & Märzinger, G. (2004). A CMOS quad-band-sigma-delta-transceiver for GSM-EDGE with dual mode transmitter architecture for low noise and high linearity. In Radio Frequency Integrated Circuits (RFIC) Symposium (pp. 431-434). Fort Worth, Texas.
MLA:
Simon, Martin, et al. "A CMOS quad-band-sigma-delta-transceiver for GSM-EDGE with dual mode transmitter architecture for low noise and high linearity." Proceedings of the Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, Texas 2004. 431-434.
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