Schmid M, Hannig F, Teich J (2012)
Publication Type: Conference contribution
Publication year: 2012
Publisher: IEEE Press
Edited Volumes: Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012
City/Town: New York, NY, USA
Pages Range: 101-108
Conference Proceedings Title: Proc. of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM)
ISBN: 978-0-7695-4699-5
DOI: 10.1109/FCCM.2012.26
We propose a novel data budget-based approach to dynamically control the average power consumption of Serial RapidIO endpoint controllers in FPGAs. The key concept of the approach is to not only perform clock-gating on the FPGA-internal components of the communication controller, but to disable the multi-gigabit transceivers during idle periods. The clock synchronization, inherent to serial interfaces, enables us to omit the often needed periodic link sensing, and only enable the controller according to a predefined schedule to transmit the allocated amount of data during a specific interval. Following this approach, we are able to reduce the dynamic power consumption by up to 77 % on average. © 2012 IEEE.
APA:
Schmid, M., Hannig, F., & Teich, J. (2012). Power Management Strategies for Serial RapidIO Endpoints in FPGAs. In Proc. of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM) (pp. 101-108). Toronto, CA: New York, NY, USA: IEEE Press.
MLA:
Schmid, Moritz, Frank Hannig, and Jürgen Teich. "Power Management Strategies for Serial RapidIO Endpoints in FPGAs." Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), Toronto New York, NY, USA: IEEE Press, 2012. 101-108.
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