Latency Hiding in Message Passing Architectures
Schröder-Preikschat W (1994)
Publication Type: Conference contribution
Publication year: 1994
Publisher: Publ by IEEE
Edited Volumes: Proceedings of the International Conference on Parallel Processing
Pages Range: 704-709
Conference Proceedings Title: Proc. of the Intern. Parallel Processing Symp.
Event location: Cancun, Mexico
URI: http://www4.informatik.uni-erlangen.de/Publications/1994/bruening_94_ipps.pdf
Abstract
The paper demonstrates the advantages of having to processors in the node of a distributed memory architecture, one for computation and one for communication. The architecture of such a dual-processor node is discussed. To exploit fully the potential for parallel execution of computation threads and communication threads, a novel, compiler-optimized IPC mechanism allows for an unbuffered no-wait send and a prefetched receive without the danger of semantics violation. It is shown how an optimized parallel operating system can be constructed such that the application processor's involvement in communication is kept to a minimum while the utilization of both processors is maximized. the MANNA implementation results in an effective message start-up latency of only 1...4 microseconds. It is also shown how the dual-processor node is utilized to efficiently realize virtual shared memory.
Authors with CRIS profile
How to cite
APA:
Schröder-Preikschat, W. (1994). Latency Hiding in Message Passing Architectures. In Proc. of the Intern. Parallel Processing Symp. (pp. 704-709). Cancun, Mexico, MX: Publ by IEEE.
MLA:
Schröder-Preikschat, Wolfgang. "Latency Hiding in Message Passing Architectures." Proceedings of the IPPS, Cancun, Mexico Publ by IEEE, 1994. 704-709.
BibTeX: Download