Roloff S, Weichslgartner A, Heißwolf J, Hannig F, Teich J (2013)
Publication Type: Conference contribution
Publication year: 2013
Publisher: ACM Press
Edited Volumes: Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems, M-SCOPES 2013
City/Town: New York, NY, USA
Pages Range: 77-85
Conference Proceedings Title: Proc. 16th International Workshop on Software and Compilers for Embedded Systems
Multi- And many-core systems become more and more mainstream and therefore new communication infrastructures like Networks-on-Chip (NoC) and new programming languages like IBM's X10 with its partitioned global address space (PGAS) are introduced. In this paper we present an X10- based simulator, which is capable to simulate the network traffic that occurs inside the X10 program. This holistic approach enables to simulate the functionality and the indicated traffic together, in contrast to pure network simulators where usually only synthetic traffic or traces are used. We explain how the communication overhead is extracted from the X10 run-time and how to simulate the NoC behavior. In experiments we show that the proposed simulator is up to 10× faster than a comparable SystemC-based simulator and at the same time preserves high accuracy. Furthermore, we present a quality and simulation speed tradeoff by using different simulation modes for a set of real world parallel applications. Copyright © 2013 ACM.
APA:
Roloff, S., Weichslgartner, A., Heißwolf, J., Hannig, F., & Teich, J. (2013). NoC Simulation in Heterogeneous Architectures for PGAS Programming Model. In Proc. 16th International Workshop on Software and Compilers for Embedded Systems (pp. 77-85). St. Goar, DE: New York, NY, USA: ACM Press.
MLA:
Roloff, Sascha, et al. "NoC Simulation in Heterogeneous Architectures for PGAS Programming Model." Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES), St. Goar New York, NY, USA: ACM Press, 2013. 77-85.
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