43 Gb/s CP-QPSK Realtime Receiver Demonstrator based on FPGAs and Block Processing

Geyer J, Fludger C, Duthel T, Presslein P, Schulien C, Schmauß B (2009)

Publication Type: Conference contribution

Publication year: 2009

Conference Proceedings Title: ECOC 2009, Vienna, Austria, 20-24 September

ISBN: 978-1-4244-5096-1

Abstract

We present measurement results of an FPGA-based 43Gb/s Realtime Coherent Receiver Demonstrator. Due to limitations we use block-aggregation and process 1/32 of the input data stream. We show back-to-back performance and chromatic dispersion tolerance.

Authors with CRIS profile

Bernhard Schmauß Professur für Hochfrequenztechnik mit dem Schwerpunkt Optische Hochfrequenztechnik und Photonik

How to cite

APA:

Geyer, J., Fludger, C., Duthel, T., Presslein, P., Schulien, C., & Schmauß, B. (2009). 43 Gb/s CP-QPSK Realtime Receiver Demonstrator based on FPGAs and Block Processing. In ECOC 2009, Vienna, Austria, 20-24 September.

MLA:

Geyer, J.C., et al. "43 Gb/s CP-QPSK Realtime Receiver Demonstrator based on FPGAs and Block Processing." Proceedings of the ECOC 2009, Vienna, Austria, 20-24 September 2009.

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