VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions

Sieh V (1997)

Publication Type: Conference contribution

Publication year: 1997

Publisher: IEEE Computer Society

City/Town: Los Alamitos

Pages Range: 32-36

Conference Proceedings Title: Proc. 27th Symposium on Fault Tolerant Computing (FTCS-27)

Event location: Seattle, WA, USA

URI: http://www3.informatik.uni-erlangen.de/Publications/Articles/sieh_ftcs27.pdf

Authors with CRIS profile

Volkmar Sieh Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme)

How to cite

APA:

Sieh, V. (1997). VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions. In Proc. 27th Symposium on Fault Tolerant Computing (FTCS-27) (pp. 32-36). Seattle, WA, USA: Los Alamitos: IEEE Computer Society.

MLA:

Sieh, Volkmar. "VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions." Proceedings of the 27th Symposium on Fault Tolerant Computing (FTCS-27), Seattle, WA, USA Los Alamitos: IEEE Computer Society, 1997. 32-36.

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