Heinrich M, Heidrich J, Ußmüller T, Weigel R (2010)
Publication Type: Conference contribution
Publication year: 2010
Publisher: IEEE
Conference Proceedings Title: IEEE International Conference on Wireless Information Technology and Systems
Event location: Honolulu, USA
ISBN: 978-1-4244-7091-4
DOI: 10.1109/ICWITS.2010.5611948
In this paper an approach for a CMOS voltage reference with the ability to calibrate both voltage over temperature behavior and absolute voltage value is presented. This is achieved by electronic controlled trimming of resistances in the PTAT current source and output amplifier. For the transistors in the PTAT current source, the diode connected reference source and the error amplifier a common size of width W = 1μm and length L = 4μm was chosen. The design has a nominal total current consumption of 3.4μA and operates at a minimum supply voltage as low as 800mV for the chosen Vref2 of 700mV. The design can be optimized for even lower current consumption by using higher resistances as well as narrower and/or longer transistors. However, such an adaption increases the chip area due to the larger size of both resistors and FETs.
APA:
Heinrich, M., Heidrich, J., Ußmüller, T., & Weigel, R. (2010). Concept For Electronic Calibration Of A CMOS Voltage Reference. In IEEE International Conference on Wireless Information Technology and Systems. Honolulu, USA: IEEE.
MLA:
Heinrich, Matthias, et al. "Concept For Electronic Calibration Of A CMOS Voltage Reference." Proceedings of the IEEE International Conference on Wireless Information Technology and Systems, Honolulu, USA IEEE, 2010.
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