A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages

Leuschner S, Pinarello S, Hodel U, Müller JE, Klar H (2010)

Publication Type: Conference contribution

Publication year: 2010

DOI: 10.1109/RFIC.2010.5477401

Authors with CRIS profile

Sandro Pinarello Lehrstuhl für Technische Elektronik

Involved external institutions

Technische Universität Berlin DE Germany (DE) Infineon Technologies AG DE Germany (DE)

How to cite

APA:

Leuschner, S., Pinarello, S., Hodel, U., Müller, J.-E., & Klar, H. (2010). A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages. In Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE.

MLA:

Leuschner, Stephan, et al. "A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages." Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE 2010.

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