Home Publications Research Grants Inventions & Patents Awards Additional Research Activities Faculties & Institutions Research Areas

A 10 mW, 4 GHz CMOS Phase-Locked Loop with Dual-Mode Tuning Technique and Partly Integrated Loop Filter

Konstanznig G, Weigel R (2003)

---

Publication Type: Conference contribution

Publication year: 2003

Pages Range: 189-192

Conference Proceedings Title: IEEE Radio Frequency Integrated Circuits Symposium

Event location: Philadelphia (Pennsylvania), USA

DOI: 10.1109/RFIC.2003.1213923

Abstract

This publication presents the design of a 4 GHz Integer-N frequency synthesizer with dual-mode tuning technique. The 3rd order loop filter is partly integrated. The intended application is a direct conversion UMTS transmitter. The design has been realized using a 0.12 μm standard CMOS-process. The proposed advanced dual-mode tuning technique is based on digital coarse-tuning with subsequent analog fine-tuning. Therefore, the voltage controlled oscillator (VCO) features both, a digital and an analog tuning interface. This results in eight equidistant frequency bands. During coarse-tuning a digital control unit selects the correct frequency band for a certain frequency channel. The remaining frequency deviation is canceled through fine tuning, which is done by a conventional charge pump phase-locked loop (PLL). This results in lower spurious emission due to the smaller VCO gain. Lock-in times of 125 μs were achieved. The output frequency can be tuned from 3.8 GHz to 4.05 GHz with a channel spacing of 400 kHz. Except for the VCO with a supply voltage of 2.2 V and a current consumption of 1.9 mA to achieve higher output swing, the synthesizer is biased at 1.5 V consuming 4 mA. Thus, the overall power consumption can be stated with 10.2 mW.

Authors with CRIS profile

How to cite

APA:

Konstanznig, G., & Weigel, R. (2003). A 10 mW, 4 GHz CMOS Phase-Locked Loop with Dual-Mode Tuning Technique and Partly Integrated Loop Filter. In IEEE Radio Frequency Integrated Circuits Symposium (pp. 189-192). Philadelphia (Pennsylvania), USA.

MLA:

Konstanznig, Georg, and Robert Weigel. "A 10 mW, 4 GHz CMOS Phase-Locked Loop with Dual-Mode Tuning Technique and Partly Integrated Loop Filter." Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia (Pennsylvania), USA 2003. 189-192.

BibTeX: Download