A Low Power 4.3 GHz Phase-Locked Loop with Advanced Dual-Mode Tuning Technique Including I/Q-Signal Generation in 0.12 um Standard CMOS
Konstanznig G, Springer A, Weigel R (2003)
Publication Type: Conference contribution
Publication year: 2003
Publisher: IEEE
Book Volume: 2
Pages Range: 288-291
Conference Proceedings Title: International Symposium on Circuits and Systems, 2003.
Event location: Bangkok, Thailand
ISBN: 978-0-7803-7761-5
DOI: 10.1109/ISCAS.2003.1205963
Abstract
The design of a 4.3 GHz Integer-N (Int-N) frequency synthesizer fabricated in a 0.12 μm standard CMOS-technology for a direct conversion UMTS receiver is reported. The fully-integrated, differential, complementary, LC-tuned voltage controlled oscillator (LC-VCO) can be tuned from 4.22 GHz to 4.34 GHz with 400 kHz steps. In order to support QPSK modulation process for the UMTS receive-band (2.11 GHz - 2.17 GHz), I/Q-signals are generated using a divide-by-two stage in master-slave configuration. The proposed advanced dual-mode tuning technique is based on digital coarse-tuning with subsequent analog fine-tuning. Coarse-tuning is controlled by an additional digital logic. The latter tuning phase is done by a conventional charge pump phase-locked loop (PLL). The 2nd order loop filter is realized off-chip. Except for the VCO with 2.3 V and a current consumption of 2 mA to achieve higher output swing, the system is biased from a 1.5 V supply consuming 8 mA. Thus, the overall power consumption can be stated to be less than 17 mW. The low power consumption compares favorable with previously published synthesizers.
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APA:
Konstanznig, G., Springer, A., & Weigel, R. (2003). A Low Power 4.3 GHz Phase-Locked Loop with Advanced Dual-Mode Tuning Technique Including I/Q-Signal Generation in 0.12 um Standard CMOS. In International Symposium on Circuits and Systems, 2003. (pp. 288-291). Bangkok, Thailand: IEEE.
MLA:
Konstanznig, Georg, Andreas Springer, and Robert Weigel. "A Low Power 4.3 GHz Phase-Locked Loop with Advanced Dual-Mode Tuning Technique Including I/Q-Signal Generation in 0.12 um Standard CMOS." Proceedings of the International Symposium on Circuits and Systems, 2003., Bangkok, Thailand IEEE, 2003. 288-291.
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