Reduced on resistance in LDMOS devices by integrating trench gates into planar technology

Erlbacher T, Bauer AJ, Frey L (2010)

Publication Status: Published

Publication Type: Journal article, Original article

Publication year: 2010

Journal

IEEE Electron Device Letters Institute of Electrical and Electronics Engineers (IEEE)

Book Volume: 31

Pages Range: 464-466

Article Number: 5437265

Journal Issue: 5

DOI: 10.1109/LED.2010.2043049

Authors with CRIS profile

Lothar Frey Lehrstuhl für Elektronische Bauelemente

Involved external institutions

Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie (IISB) DE Germany (DE)

How to cite

APA:

Erlbacher, T., Bauer, A.J., & Frey, L. (2010). Reduced on resistance in LDMOS devices by integrating trench gates into planar technology. IEEE Electron Device Letters, 31(5), 464-466. https://doi.org/10.1109/LED.2010.2043049

MLA:

Erlbacher, Tobias, Anton J. Bauer, and Lothar Frey. "Reduced on resistance in LDMOS devices by integrating trench gates into planar technology." IEEE Electron Device Letters 31.5 (2010): 464-466.

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